View AD8132ARZ-R7_3268609.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low cost, high speed differential amplifier ad8132 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features high speed 350 mhz, ?3 db bandwidth 1200 v/s slew rate resistor set gain internal common-mode feedback improved gain and phase balance ?68 db @ 10 mhz separate input to set the common-mode output voltage low distortion: ?99 dbc sfdr @ 5 mhz, 800 load low power: 10.7 ma @ 5 v power supply range: +2.7 v to 5.5 v applications low power differential adc drivers differential gain and differential filtering video line drivers differential in/out level shifting single-ended input to differential output drivers active transformers general description the ad8132 is a low cost differential or single-ended input to differential output amplifier with resistor set gain. the ad8132 is a major advancement over op amps for driving differential input adcs or for driving signals over long lines. the ad8132 has a unique internal feedback feature that provides output gain and phase matching balanced to ?68 db at 10 mhz, suppressing harmonics and reducing radiated emi. manufactured using the next generation of analog devices, inc.s xfcb bipolar process, the ad8132 has a ?3 db bandwidth of 350 mhz and delivers a differential signal with ?99 dbc sfdr at 5 mhz, despite its low cost. the ad8132 eliminates the need for a transformer with high performance adcs, preserving the low frequency and dc information. the common-mode level of the differential output is adjustable by applying a voltage on the v ocm pin, easily level shifting the input signals for driving single-supply adcs. fast overload recovery preserves sampling accuracy. pin configuration ?in 1 v ocm 2 v+ 3 +out 4 +in 8 nc 7 v? 6 ?out 5 nc = no connect ad8132 01035-001 figure 1. the ad8132 is also used as a differential driver for the trans- mission of high speed signals over low cost twisted pair or coaxial cables. the feedback network can be adjusted to boost the high frequency components of the signal. the ad8132 is used for either analog or digital video signals or for other high speed data trans- mission. the ad8132 is capable of driving either a category 3 or category 5 twisted pair or coaxial cable with minimal line attenuation. the ad8132 has considerable cost and performance improvements over discrete line driver solutions. differential signal processing reduces the effects of ground noise that plagues ground-referenced systems. the ad8132 can be used for differential signal processing (gain and filtering) through- out a signal chain, easily simplifying the conversion between differential and single-ended components. the ad8132 is available in both soic_n and msop packages for operation over the extended industrial temperature range of ?40c to +125c. frequency (mhz) 6 1 gain (db) 3 0 ?3 ?6 ?9 ?12 10 100 1k v s = 5v g = +1 v o, dm = 2v p-p r l, dm = 499 ? 01035-002 figure 2. large signal frequency response
ad8132 rev. f | page 2 of 32 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 pin configuration............................................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 d in to out specifications...................................................... 3 v ocm to out specifications ..................................................... 4 d in to out specifications...................................................... 5 v ocm to out specifications ..................................................... 6 d in to out specifications...................................................... 7 v ocm to out specifications ..................................................... 7 absolute maximum ratings............................................................ 8 thermal resistance ...................................................................... 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 typical performance characteristics ........................................... 10 test circuits..................................................................................... 19 operational description................................................................ 20 definition of terms.................................................................... 20 basic circuit operation ............................................................. 20 theory of operation ...................................................................... 21 general usage of the ad8132 .................................................. 21 differential amplifier without resistors (high input impedance inverting amplifier) .............................................. 21 other 2 = 1 circuits ................................................................. 22 varying 2 ................................................................................... 22 1 = 0............................................................................................ 22 estimating the output noise voltage ...................................... 22 calculating input impedance of the application circuit ..... 23 input common-mode voltage range in single-supply applications ................................................................................ 23 setting the output common-mode voltage .......................... 23 driving a capacitive load......................................................... 23 open-loop gain and phase ..................................................... 23 layout, grounding, and bypassing.............................................. 24 circuits......................................................................................... 24 applications..................................................................................... 25 analog-to-digital driver .......................................................... 25 balanced cable driver............................................................... 25 transmit equalizer ..................................................................... 26 low-pass differential filter ...................................................... 26 high common-mode output impedance amplifier ........... 27 full-wave rectifier .................................................................... 28 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 29 revision history 11/06rev. e to rev. f updated format..................................................................universal changes to table 1............................................................................ 3 changes to table 4............................................................................ 6 changes to table 5............................................................................ 7 changes to ordering guide .......................................................... 29 11/05rev. d to rev. e changes to table 7, thermal resistance section, maximum power dissipation section, and figure 3....................................... 8 changes to ordering guide .......................................................... 29 12/04rev. c to rev. d changes to general description .....................................................1 changes to specifications.................................................................2 changes to absolute maximum ratings........................................8 updated outline dimensions....................................................... 29 changes to ordering guide .......................................................... 29 2/03rev. b to rev. c changes to specifications.................................................................2 addition to estimating the output noise voltage section....... 15 updated outline dimensions....................................................... 21 1/02rev. a to rev. b edits to transmitter equalizer section........................................ 18
ad8132 rev. f | page 3 of 32 specifications d in to out specifications at t a = 25c, v s = 5 v, v ocm = 0 v, g = 1, r l, dm = 499 , r f = r g = 348 , unless otherwise noted. for g = 2, r l, dm = 200 , r f = 1000 , r g = 499 . refer to figure 56 and figure 57 for test setup and label descriptions. all specifications refer to single-ended inpu t and differential outputs, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance ?3 db large signal bandwidth v out = 2 v p-p 300 350 mhz v out = 2 v p-p, g = 2 190 mhz ?3 db small signal bandwidth v out = 0.2 v p-p 360 mhz v out = 0.2 v p-p, g = 2 160 mhz bandwidth for 0.1 db flatness v out = 0.2 v p-p 90 mhz v out = 0.2 v p-p, g = 2 50 mhz slew rate v out = 2 v p-p 1000 1200 v/s settling time 0.1%, v out = 2 v p-p 15 ns overdrive recovery time v in = 5 v to 0 v step, g = 2 5 ns noise/harmonic performance second harmonic v out = 2 v p-p, 1 mhz, r l, dm = 800 ?96 dbc v out = 2 v p-p, 5 mhz, r l, dm = 800 ?83 dbc v out = 2 v p-p, 20 mhz, r l, dm = 800 ?73 dbc third harmonic v out = 2 v p-p, 1 mhz, r l, dm = 800 ?102 dbc v out = 2 v p-p, 5 mhz, r l, dm = 800 ?98 dbc v out = 2 v p-p, 20 mhz, r l, dm = 800 ?67 dbc imd 20 mhz, r l, dm = 800 ?76 dbc ip3 20 mhz, r l, dm = 800 40 dbm input voltage noise (rti) f = 0.1 mhz to 100 mhz 8 nv/hz input current noise f = 0.1 mhz to 100 mhz 1.8 pa/hz differential gain error ntsc, g = 2, r l, dm = 150 0.01 % differential phase error ntsc, g = 2, r l, dm = 150 0.10 degrees input characteristics offset voltage (rti) v os, dm = v out, dm /2; v din+ = v din? = v ocm = 0 v 1.0 3.5 mv t min to t max variation 10 v/c input bias current 3 7 a input resistance differential 12 m common mode 3.5 m input capacitance 1 pf input common-mode voltage ?4.7 to +3.0 v cmrr v out, dm /v in, cm ; v in, cm = 1 v; resistors matched to 0.01% ?70 ?60 db output characteristics output voltage swing maximum v out ; single-ended output ?3.6 to +3.6 v output current +70 ma output balance error v out, cm /v out, dm ; v out, dm = 1 v ?70 db
ad8132 rev. f | page 4 of 32 v ocm to out specifications at t a = 25c, v s = 5 v, v ocm = 0 v, g = 1, r l, dm = 499 , r f = r g = 348 , unless otherwise noted. for g = 2, r l, dm = 200 , r f = 1000 , r g = 499 . refer to figure 56 and figure 57 for test setup and label descriptions. all specifications refer to single-ended inpu t and differential outputs, unless otherwise noted. table 2. parameter conditions min typ max unit dynamic performance ?3 db bandwidth v ocm = 600 mv p-p 210 mhz slew rate v ocm = ?1 v to +1 v 400 v/s input voltage noise (rti) f = 0.1 mhz to 100 mhz 12 nv/hz dc performance input voltage range 3.6 v input resistance 50 k input offset voltage v os, cm = v out, cm ; v din+ = v din? = v ocm = 0 v 1.5 7 mv input bias current 0.5 a v ocm cmrr v out, dm /v ocm ; v ocm = 1 v; resistors matched to 0.01% ?68 db gain v out, cm /v ocm ; v ocm = 1 v 0.985 1 1.015 v/v power supply operating range 1.35 5.5 v quiescent current v din+ = v din? = v ocm = 0 v 11 12 13 ma t min to t max variation 16 a/c power supply rejection ratio v out, dm /v s ; v s = 1 v ?70 ?60 db operating temperature range ?40 +125 c
ad8132 rev. f | page 5 of 32 d in to out specifications at t a = 25c, v s = 5 v, v ocm = 2.5 v, g = 1, r l, dm = 499 , r f = r g = 348 , unless otherwise noted. for g = 2, r l, dm = 200 , r f = 1000 , r g = 499 . refer to figure 56 and figure 57 for test setup and label descriptions. all specifications refer to single-ended inpu t and differential outputs, unless otherwise noted. table 3. parameter conditions min typ max unit dynamic performance ?3 db large signal bandwidth v out = 2 v p-p 250 300 mhz v out = 2 v p-p, g = 2 180 mhz ?3 db small signal bandwidth v out = 0.2 v p-p 360 mhz v out = 0.2 v p-p, g = 2 155 mhz bandwidth for 0.1 db flatness v out = 0.2 v p-p 65 mhz v out = 0.2 v p-p, g = 2 50 mhz slew rate v out = 2 v p-p 800 1000 v/s settling time 0.1%, v out = 2 v p-p 20 ns overdrive recovery time v in = 2.5 v to 0 v step, g = 2 5 ns noise/harmonic performance second harmonic v out = 2 v p-p, 1 mhz, r l, dm = 800 ?97 dbc v out = 2 v p-p, 5 mhz, r l, dm = 800 ?100 dbc v out = 2 v p-p, 20 mhz, r l, dm = 800 ?74 dbc third harmonic v out = 2 v p-p, 1 mhz, r l, dm = 800 ?100 dbc v out = 2 v p-p, 5 mhz, r l, dm = 800 ?99 dbc v out = 2 v p-p, 20 mhz, r l, dm = 800 ?67 dbc imd 20 mhz, r l, dm = 800 ?76 dbc ip3 20 mhz, r l, dm = 800 40 dbm input voltage noise (rti) f = 0.1 mhz to 100 mhz 8 nv/hz input current noise f = 0.1 mhz to 100 mhz 1.8 pa/hz differential gain error ntsc, g = 2, r l, dm = 150 0.025 % differential phase error ntsc, g = 2, r l, dm = 150 0.15 degrees input characteristics offset voltage (rti) v os, dm = v out, dm /2; v din+ = v din? = v ocm = 2.5 v 1.0 3.5 mv t min to t max variation 6 v/c input bias current 3 7 a input resistance differential 10 m common-mode 3 m input capacitance 1 pf input common-mode voltage 0.3 to 3.0 v cmrr v out, dm /v in, cm ; v in, cm = 1 v; resistors matched to 0.01% ?70 ?60 db output characteristics output voltage swing maximum v out ; single-ended output 1.0 to 4.0 v output current 50 ma output balance error v out, cm /v out, dm ; v out, dm = 1 v ?68 db
ad8132 rev. f | page 6 of 32 v ocm to out specifications at t a = 25c, v s = 5 v, v ocm = 2.5 v, g = 1, r l, dm = 499 , r f = r g = 348 , unless otherwise noted. for g = 2, r l, dm = 200 , r f = 1000 , r g = 499 . refer to figure 56 and figure 57 for test setup and label descriptions. all specifications refer to single-ended inpu t and differential outputs, unless otherwise noted. table 4. parameter conditions min typ max unit dynamic performance ?3 db bandwidth v ocm = 600 mv p-p 210 mhz slew rate v ocm = 1.5 v to 3.5 v 340 v/s input voltage noise (rti) f = 0.1 mhz to 100 mhz 12 nv/hz dc performance input voltage range 1.0 to 3.7 v input resistance 30 k input offset voltage v os, cm = v out, cm ; v din+ = v din? = v ocm = 2.5 v 5 11 mv input bias current 0.5 a v ocm cmrr v out, dm /v ocm ; v ocm = 2.5 v 1 v; resistors matched to 0.01% ?66 db gain v out, cm /v ocm ; v ocm = 2.5 v 1 v 0.985 1 1.015 v/v power supply operating range 2.7 11 v quiescent current v din+ = v din? = v ocm = 2.5 v 9.4 10.7 12 ma t min to t max variation 10 a/c power supply rejection ratio v out, dm /v s ; v s = 1 v ?70 ?60 db operating temperature range ?40 +125 c
ad8132 rev. f | page 7 of 32 d in to out specifications at t a = 25c, v s = 3 v, v ocm = 1.5 v, g = 1, r l, dm = 499 , r f = r g = 348 , unless otherwise noted. for g = 2, r l, dm = 200 , r f = 1000 , r g = 499 . refer to figure 56 and figure 57 for test setup and label descriptions. all specifications refer to single-ended inpu t and differential outputs, unless otherwise noted. table 5. parameter conditions min typ max unit dynamic performance ?3 db large signal bandwidth v out = 1 v p-p 350 mhz v out = 1 v p-p, g = 2 165 mhz ?3 db small signal bandwidth v out = 0.2 v p-p 350 mhz v out = 0.2 v p-p, g = 2 150 mhz bandwidth for 0.1 db flatness v out = 0.2 v p-p 45 mhz v out = 0.2 v p-p, g = 2 50 mhz noise/harmonic performance second harmonic v out = 1 v p-p, 1 mhz, r l, dm = 800 ?100 dbc v out = 1 v p-p, 5 mhz, r l, dm = 800 ?94 dbc v out = 1 v p-p, 20 mhz, r l, dm = 800 ?77 dbc third harmonic v out = 1 v p-p, 1 mhz, r l, dm = 800 ?90 dbc v out = 1 v p-p, 5 mhz, r l, dm = 800 ?85 dbc v out = 1 v p-p, 20 mhz, r l, dm = 800 ?66 dbc input characteristics offset voltage (rti) v os, dm = v out, dm /2; v din+ = v din? = v ocm = 1.5 v 10 mv input bias current 3 a input common-mode voltage 0.3 to 1.0 v cmrr v out, dm /v in, cm ; v in, cm = 0.5 v; resistors matched to 0.01% ?60 db v ocm to out specifications at t a = 25c, v s = 3 v, v ocm = 1.5 v, g = 1, r l, dm = 499 , r f = r g = 348 , unless otherwise noted. for g = 2, r l, dm = 200 , r f = 1000 , r g = 499 . refer to figure 56 and figure 57 for test setup and label descriptions. all specifications refer to single-ended inpu t and differential outputs, unless otherwise noted. table 6. parameter conditions min typ max unit dc performance input offset voltage v os, cm = v out, cm ; v din+ = v din? = v ocm = 1.5 v 7 mv gain v out, cm /v ocm ; v ocm = 0.5 v 1 v/v power supply operating range 2.7 11 v quiescent current v din+ = v din? = v ocm = 0 v 7.25 ma power supply rejection ratio v out, dm /v s ; v s = 0.5 v ?70 db operating temperature range ?40 +125 c
ad8132 rev. f | page 8 of 32 absolute maximum ratings table 7. parameter rating supply voltage 5.5 v v ocm v s internal power dissipation 250 mw operating temperature range ?40c to +125c storage temperature range ?65c to +150c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, ja is specified for the device soldered in a circuit board in still air. table 8. package type ja unit 8-lead soic/4-layer 121 c/w 8-lead msop/4-layer 142 c/w maximum power dissipation the maximum safe power dissipation in the ad8132 packages is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c (the glass transition temperature), the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ad8132. exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the load current consists of the dif- ferential and common-mode currents flowing to the load, as well as currents flowing through the external feedback net- works and the internal common-mode feedback loop. the internal resistor tap used in the common-mode feedback loop places a 1 k differential load on the output. consider rms voltages and currents when dealing with ac signals. airflow reduces ja . in addition, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the ja . figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead soic_n ( ja = 121c/w) and msop ( ja = 142c/w) packages on a jedec standard 4-layer board. ja values are approximations. ambient temperature (c) maximum power dissip a tion (w) 1.75 1.50 1.00 1.25 0.50 0.25 0.75 0 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 110 120 soic msop 01035-082 figure 3. maximum power dissipation vs. temperature esd caution
ad8132 rev. f | page 9 of 32 pin configuration and fu nction descriptions ?in 1 v ocm 2 v+ 3 +ou t 4 +in 8 nc 7 v? 6 ?out 5 nc = no connect ad8132 01035-004 figure 4. pin configuration table 9. pin function descriptions pin no. mnemonic description 1 ?in negative input. 2 v ocm voltage applied to this pin sets the common-mo de output voltage with a ratio of 1:1. for example, 1 v dc on v ocm sets the dc bias level on +out and ?out to 1 v. 3 v+ positive supply voltage. 4 +out positive output. note that the voltage at ?d in is inverted at +out (see figure 64). 5 ?out negative output. note that the voltage at +d in is inverted at ?out (see figure 64). 6 v? negative supply voltage. 7 nc no connect. 8 +in positive input.
ad8132 rev. f | page 10 of 32 typical performance characteristics frequency (mhz) gain (db) 2 1 1 0 ? 1 ? 2 ? 3 ? 4 ? 5 10 100 1k g = +1 v o, dm = 0.2v p-p r l, dm = 499 ? v s = +3v v s = +5v v s = 5v 01035-006 figure 5. small signal frequency response (see figure 56) frequency (mhz) gain (db) 1 10 100 1k 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0.5 g = +1 v o, dm = 0.2v p-p r l, dm = 499 ? v s = +3v v s = +5v v s = 5v 01035-007 figure 6. 0.1 db flatness vs. frequency; c f = 0 pf (see figure 56) frequency (mhz) gain (db) 1 10 100 1k g = +1 v o, dm = 0.2v p-p r l, dm = 499 ? 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 v s = +3v v s = +5v v s = 5v 01035-008 figure 7. 0.1 db flatness vs. frequency; c f = 0.5 pf (see figure 56) frequency (mhz) gain (db) 1 10 100 1k 2 1 0 ? 1 ? 2 ? 3 ? 4 ? 5 3 g = +1 v o, dm = 2v p-p for v s = 5v, +5v v o, dm = 1v p-p for v s = +3v r l, dm = 499 ? v s = +3v v s = +5v v s = 5v v s = +3v 01035-009 figure 8. large signal frequency response; c f = 0 pf (see figure 56) frequency (mhz) gain (db) 1101001k 2 1 0 ?1 ?2 ?3 ?4 ?5 g = +1 v o, dm = 2v p-p for v s = 5v, +5v v o, dm = 1v p-p for v s = +3v r l, dm = 499 ? v s = +3v v s = +5v v s = 5v v s = +3v 01035-010 figure 9. large signal frequency response; c f = 0.5 pf (see figure 56) frequency (mhz) gain (db) 1101001k 2 1 0 ?1 ?2 ?3 ?4 ?5 3 v s = 5v g = +1 v o, dm = 2v p-p r l, dm = 499 ? ?40c +85c +25c 01035-011 figure 10. large signal frequency response at various temperatures (see figure 56)
ad8132 rev. f | page 11 of 32 frequency (mhz) gain (db) 1101001k 2 1 0 ?1 ?2 ?3 ?4 ?5 3 v s = 5v g = +1 v o, dm = 2v p-p r l, dm = 499 ? r f = 499 ? r f = 348 ? r f = 249 ? 01035-012 figure 11. large signal frequency response vs. r f (see figure 56) frequency (mhz) impedance ( ? ) 100 1 10 1 0.1 10 100 v s = +5v v s = 5v 01035-013 figure 12. closed-loop single-ended z out vs. frequency; g = 1 (see figure 56) frequency (mhz) gain (db) 7 1 6 5 4 3 2 1 10 100 1k g = +2 v o, dm = 0.2v p-p r l, dm = 200 ? v s = +3v v s = 5v, +5v 01035-015 figure 13. small signal frequency response (see figure 57) frequency (mhz) gain (db) 1 10 100 1k v s = +3v, +5v, 5v g = +2 v o, dm = 0.2v p-p r l, dm = 200 ? 6.1 6.0 5.9 5.8 5.7 5.6 5.5 01035-016 figure 14. 0.1 db flatness vs. frequency (see figure 57) frequency (mhz) gain (db) 1101001k 7 6 5 4 3 2 1 v s = +5v, 5v v s = +3v g = +2 v o, dm = 2v p-p for v s = 5v, +5v v o, dm = 1v p-p for v s = +3v r l, dm = 200 ? 01035-017 figure 15. large signal frequency response (see figure 57) frequency (mhz) gain (db) 1 10 100 1k 7 6 5 4 3 2 1 v s = 5v g = +2 v o, dm = 0.2v p-p r l, dm = 200 ? r f = 1.0k ? r f = 499 ? r f = 1.5k ? 01035-018 figure 16. small signal frequency response vs. r f (see figure 57)
ad8132 rev. f | page 12 of 32 frequency (mhz) gain (db) 1101001k 25 20 15 10 5 0 ?5 v s = 5v v o, dm = 2v p-p r l, dm = 200 ? r g = 499 ? ?10 ?15 01035-020 g = +10, r f = 4.99k ? g = +5, r f = 2.49k ? g = +2, r f = 1k ? g = +1, r f = 499 ? figure 17. large signal frequency response for various gains (see figure 58) frequency (mhz) rti balance error (db) 1 10 100 1k ? 25 ?30 ?35 ?40 ?45 ?50 ?55 v s = 5v v o, dm = 2v p-p v o, cm / v o, dm ?60 ?65 g = 1 g = 2 ?70 ?75 01035-022 figure 18. rti output balance error vs. frequency (see figure 59) frequency (mhz) distortion (dbc) 0 506070 ? 40 ?50 ?60 ?70 ?80 ?90 ?100 20 30 40 10 ?110 r l, dm = 800 ? v o, dm = 1v p-p hd3 (v s = 3v) hd2 (v s = 3v) hd2 (v s = 5v) hd3 (v s = 5v) 01035-024 figure 19. harmonic distortion vs . frequency, g = 1 (see figure 62) frequency (mhz) distortion (dbc) 0506070 ?40 ?50 ?60 ?70 ?80 ?90 ?100 20 30 40 10 ?110 r l, dm = 800 ? v o, dm = 2v p-p hd3 (v s = +5v) hd2 (v s = 5v) hd2 (v s = +5v) hd3 (v s = 5v) ? 30 01035-025 figure 20. harmonic distortion vs . frequency, g = 1 (see figure 62) differential output voltage (v p-p) distortion (dbc) 0.25 1.50 1.75 ? 40 ?50 ?60 ?70 ?80 ?90 ?100 0.75 1.00 1.25 0.50 ?110 v s = 3v r l, dm = 800 ? hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 01035-026 figure 21. harmonic distortion vs. differential output voltage, g = 1 (see figure 62) differential output voltage (v p-p) distortion (dbc) 0 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 234 1 ? 110 v s = 5v r l, dm = 800 ? hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 01035-027 figure 22. harmonic distortion vs. differential output voltage, g = 1 (see figure 62)
ad8132 rev. f | page 13 of 32 differential output voltage (v p-p) distortion (dbc) 0 ? 40 ?50 ?60 ?70 ?80 ?90 ?100 234 1 ?110 v s = 5v r l, dm = 800 ? hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 5 6 01035-028 figure 23. harmonic distortion vs. differential output voltage, g = 1 (see figure 62) r load ( ? ) distortion (dbc) 200 700 800 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 400 500 600 300 ? 110 v s = 3v v o, dm = 1v p-p 900 1000 hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 01035-029 figure 24. harmonic distortion vs. r load , g = 1 (see figure 62) r load ( ? ) distortion (dbc) 200 700 800 ? 50 ?60 ?70 ?80 ?90 ?100 400 500 600 300 ?110 v s = 5v v o, dm = 2v p-p 900 1000 hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 01035-030 figure 25. harmonic distortion vs. r load , g = 1 (see figure 62) r load ( ? ) distortion (dbc) 200 700 800 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 400 500 600 300 ? 110 v s = 5v v o, dm = 2v p-p hd3 (f = 20mhz) hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 900 1000 01035-031 figure 26. harmonic distortion vs. r load , g = 1 (see figure 62) frequency (mhz) distortion (dbc) 40 50 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 10 20 30 0 ? 110 hd3 (v s = 3v) 60 70 r l, dm = 800 ? v o, dm = 1v p-p ? 40 hd3 (v s = 5v) hd2 (v s = 5v) hd2 (v s = 3v) 01035-033 figure 27. harmonic distortion vs . frequency, g = 2 (see figure 63) frequency (mhz) distortion (dbc) 40 50 ?50 ?60 ?70 ?80 ?90 ?100 10 20 30 0 hd3 (v s = 5v) 60 70 r l, dm = 800 ? v o, dm = 4v p-p ?40 hd3 (v s = +5v) hd2 (v s = +5v) 80 ?30 ? 20 hd2 (v s = 5v) 01035-034 figure 28. harmonic distortion vs . frequency, g = 2 (see figure 63)
ad8132 rev. f | page 14 of 32 differential output voltage (v p-p) distortion (dbc) 2 ?50 ?60 ?70 ?80 ?90 ?100 1 03 v s = 5v r l, dm = 800 ? ? 40 hd3 (f = 20mhz) 4 ?110 ?120 hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 01035-035 figure 29. harmonic distortion vs. differential output voltage, g = 2 (see figure 63) differential output voltage (v p-p) distortion (dbc) 2 ?50 ?60 ?70 ?80 ?90 ?100 1 03 v s = 5v r l, dm = 800 ? ? 40 hd3 (f = 20mhz) 4 ?110 hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 56 01035-036 figure 30. harmonic distortion vs. differential output voltage, g = 2 (see figure 63) r load ( ? ) distortion (dbc) 400 ? 50 ?60 ?70 ?80 ?90 ?100 300 200 500 hd3 (f = 20mhz) 600 ?110 hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 700 800 v s = 5v v o, dm = 2v p-p 900 1000 01035-037 figure 31. harmonic distortion vs. r load , g = 2 (see figure 63) r load ( ? ) distortion (dbc) 400 ? 50 ?60 ?70 ?80 ?90 ?100 300 200 500 hd3 (f = 20mhz) 600 ?110 hd2 (f = 20mhz) hd2 (f = 5mhz) hd3 (f = 5mhz) 700 800 v s = 5v v o, dm = 2v p-p 900 1000 01035-038 figure 32. harmonic distortion vs. r load , g = 2 (see figure 63) frequency (mhz) p out (dbm [re: 50 ? ]) 10 19.5 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 20.0 20.5 f c = 20mhz v s = 5v r l, dm = 800 ? 01035-039 figure 33. intermodulation distortion, g = 1 frequency (mhz) 45 15 010 70 20 30 40 50 60 40 35 30 25 20 v s = 5v, +5v r l, dm = 800 ? intercept (dbm [re: 50 ? ]) 01035-040 figure 34. third-order intercept vs. frequency, g = 1
ad8132 rev. f | page 15 of 32 v s = 5v, +5v, +3v 40mv 5ns 01035-041 figure 35. small signal transient response, g = 1 300mv 5ns v s = 3v v o, dm = 1.5v p-p c f = 0pf c f = 0.5pf 0 1035-042 figure 36. large signal transient response, g = 1 400mv 5ns v s = 5v v o, dm = 2v p-p c f = 0pf c f = 0.5pf 0 1035-043 figure 37. large signal transient response, g = 1 v s = 5v v o, dm = 2v p-p 400mv 5ns c f = 0pf c f = 0.5pf 01035-044 figure 38. large signal transient response, g = 1 1v 5ns v ? out v +out v +din v o, dm 01035-045 figure 39. large signal transient response, g = 1 40mv 5ns v s = 5v, +5v, +3v 01035-046 figure 40. small signal transient response, g = 2
ad8132 rev. f | page 16 of 32 300mv 5ns v s = 3v 01035-047 figure 41. large signal transient response, g = 2 400mv 5ns v s = +5v, 5v 01035-048 figure 42. large signal transient response, g = 2 1v 5ns v s = 5v v o, dm v ?out v +out v +din 01035-049 figure 43. large signal transient response, g = 2 2mv 5ns v s = 5v g = +1 v o, dm = 2v p-p r l, dm = 499 ? 5ns/div 0.1%/div 0 5 10 15 20 25 30 35 40 01035-050 figure 44. 0.1% settling time 5ns c l = 5pf c l = 0pf c l = 20pf 400mv 01035-052 figure 45. large signal transient response for various capacitor loads (see figure 60) frequency (mhz) psrr (db) 0.1 1 10 100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 1k v o, dm v s +psrr ?psrr +psrr (v s = 5v, +5v) ?psrr (v s = 5v) 01035-053 figure 46. psrr vs. frequency
ad8132 rev. f | page 17 of 32 frequency (mhz) cmrr (db) 1 10 100 1000 ?70 ?80 ?50 ?60 ?30 ?40 ? 20 v o, dm v in, cm v o, cm v in, cm v s = 5v v in, cm = 2v p-p 01035-055 figure 47. cmrr vs. frequency (see figure 61) frequency (mhz) v ocm gain (db) 1 10 100 1000 ?9 ?12 ?3 ?6 0 v o, cm v ocm v ocm = 600mv p-p v ocm = 2v p-p 3 6 ?15 v s = 5v 01035-056 figure 48. v ocm gain response v s = 5v v ocm = ?1v to +1v 400mv 5ns v o, cm 01035-057 figure 49. v ocm transient response frequency (mhz) v ocm cmrr (db) 1 10 100 1000 ?70 ?80 ?50 ?60 ?30 ?40 ?20 v ocm = 2v p-p v ocm = 600mv p-p v o, dm v ocm ? 10 01035-058 figure 50. v ocm cmrr vs. frequency frequency (hz) input voltage noise (nv/ 01035-059 8nv/ hz figure 51. input voltage noise vs. frequency frequency (hz) 1k 10 100 10 1 100 1k 10k 100k 1m 10m 100m input current noise (pa/ 01035-060 1.8pa/ hz figure 52. input current noise vs. frequency
ad8132 rev. f | page 18 of 32 5ns v o, dm (0.5v/div) v in, sm (1v/div) v s = 5v v in = 2.5v step g = +2 r f = 1k ? r l, dm = 200 ? 01035-061 figure 53. over drive recovery temperature (c) supply current (ma) 15 13 5 ?50 ?30 90 ?1010305070 11 9 7 v s = 5v v s = +5v 01035-062 figure 54. quiescent current vs. temperature temperature (c) differenti a l output offset (mv) 0 ?0.5 ?2.5 ?40 ?20 100 020406080 ?1.0 ?1.5 ?2.0 v s = 5v v s = +5v 01035-063 figure 55. differential output offset voltage vs. temperature
ad8132 rev. f | page 19 of 32 test circuits 0.1f 348 ? 348 ? 49.9 ? 24.9 ? 348 ? 348 ? 499 ? c f c f 01035-005 figure 56. basic test circuit, g = 1 0.1f 499 ? 499 ? 49.9 ? 24.9 ? 1000 ? 1000 ? 200 ? 01035-014 figure 57. basic test circuit, g = 2 0.1f 499 ? 499 ? 49.9 ? 24.9 ? r f 200 ? r f 01035-019 figure 58. test circuit for various gains 0.1f 49.9 ? 24.9 ? r f r f r g r g r l r l g = +1: r f = r g = 348 ? , r l = 249 ? (r l, dm = 498 ? ) g = +2: r f = 1000 ? , r g = 499 ? , r l = 100 ? (r l, dm = 200 ? ) 01035-021 figure 59. test circuit for output balance 0.1f 348 ? 348 ? 49.9 ? 24.9 ? 348 ? 348 ? 453 ? 24.9 ? 24.9 ? c l 01035-051 figure 60. test circuit for capacitor load drive 348 ? 348 ? 49.9 ? 348 ? 348 ? 249 ? 249 ? v o, dm v o, cm notes resistors matched to 0.01%. 01035-054 figure 61. cmrr test circuit 0.1f 348 ? 348 ? 49.9 ? 24.9 ? 348 ? 348 ? 300 ? 300 ? 2:1 transformer lpf hpf z in = 50 ? 01035-023 figure 62. harmonic distortion test circuit, g = 1, r l, dm = 800 0.1f 499 ? 499 ? 49.9 ? 24.9 ? 1000 ? ? 300 ? 300 ? 2:1 transformer lpf hpf z in = 50 ? 01035-032 figure 63. harmonic distortion test circuit, g = 2, r l, dm = 800
ad8132 rev. f | page 20 of 32 operational description definition of terms differential voltage the difference between two node voltages. for example, the output differential voltage (or equivalently output differential- mode voltage) is defined as v out, dm = ( v +out ? v ?out ) where v +out and v ?out refer to the voltages at the +out and ?out terminals with respect to a common reference. common-mode voltage the average of two node voltages. the output common-mode voltage is defined as v out, cm = ( v +out + v ?out )/2 ad8132 c f +in ?in r f c f r f r g r g +d in v ocm ?d in r l, dm +out v o, dm ?out 0 1035-064 figure 64. circuit definitions basic circuit operation one of the more useful and easy to understand ways to use the ad8132 is to provide two equal-ratio feedback networks. to match the effect of parasitics, comprise these networks of two equal-value feedback resistors (r f ) and two equal-value gain resistors (r g ). this circuit is shown in figure 64. like a conventional op amp, the ad8132 has two differential inputs that can be driven with both differential-mode input voltage (v in, dm ) and common-mode input voltage (v in, cm ). there is another input (v ocm ) that is not present on conventional op amps, but provides another input to consider on the ad8132. it is totally separate from the previous inputs. there are two complementary outputs whose response can be defined by a differential-mode output (v out, dm ) and a common- mode output (v out, cm ). table 10 indicates the gain from any type of input to either type of output. table 10. differential and common-mode gains input v out, dm v out, cm v in, dm r f /r g 0 (by design) v in, cm 0 0 (by design) v ocm 0 1 (by design) as listed in table 10, the differential output (v out, dm ) is equal to the differential input voltage (v in, dm ) times rf/rg. in this case, it does not matter if both differential inputs are driven, or only one output is driven and the other is tied to a reference voltage, such as ground. as seen from the two zero entries in the v out, dm column, neither of the common-mode inputs has any effect on this gain. the gain from v in, dm to v out, cm is 0, and first-order does not depend on the ratio matching of the feedback networks. the common-mode feedback loop within the ad8132 provides a cor- rective action to keep this gain term minimized. the term balance error describes the degree that this gain term differs from 0. the gain from v in, cm to v out, dm directly depends on the matching of the feedback networks. the analogous term for this transfer function (used in conventional op amps) is common-mode reject- tion ratio (cmrr). therefore, if it has a high cmrr, the feedback ratios must be well matched. the gain from v in, cm to v out, cm is ideally 0 and is first-order independent of the feedback ratio matching. as in the case of v in, dm to v out, cm , the common-mode feedback loop keeps this term minimized. the gain from v ocm to v out, dm is ideally 0 when the feedback ratios are matched only. the amount of differential output signal that is created by varying v ocm is related to the degree of mismatch in the feedback networks. v ocm controls the output common-mode voltage v out, cm with a unity-gain transfer function. with equal-ratio feedback net- works (as previously assumed), its effect on each output is the same, that is the gain from v ocm to v out, dm is 0. if not driven, the output common-mode voltage is set with an internal voltage divider to a level that is nominally midsupply. it is recommended that a 0.1 f bypass capacitor be connected to v ocm . when unequal feedback ratios are used, the two gains associated with v out, dm become nonzero. this significantly complicates the mathematical analysis along with any intuitive understanding of how the part operates.
ad8132 rev. f | page 21 of 32 theory of operation the ad8132 differs from conventional op amps by the external presence of an additional input and output. the additional input, v ocm , controls the output common-mode voltage. the additional output is the analog complement of the single output of a conven- tional op amp. for its operation, the ad8132 uses two feedback loops as compared to the single loop of conventional op amps. although this provides significant freedom to create various novel circuits, basic op amp theory can still be used to analyze the operation. one of the feedback loops controls the output common-mode voltage, v out, cm . its input is v ocm (pin 2) and the output is the common-mode, or average voltage, of the two differential outputs (+out and ?out). the gain of this circuit is internally set to unity. when the ad8132 is operating in its linear region, this establishes one of the operational constraints: v out, cm = v ocm . the second feedback loop controls the differential operation. similar to an op amp, the gain and gain shaping of the transfer function can be controlled by adding passive feedback networks. however, only one feedback network is required to close the loop and fully constrain the operation, but depending on the function desired, two feedback networks can be used. this is possible because there are two outputs that are each inverted with respect to the differential inputs. general usage of the ad8132 several assumptions are made here for a first-order analysis; they are the typical assumptions used for the analysis of op amps: ? the input bias currents are sufficiently small so they can be neglected. ? the output impedances are arbitrarily low. ? the open-loop gain is arbitrarily large, and drives the amplifier to a state where the input differential voltage is effectively 0. ? offset voltages are assumed to be 0. though it is possible to operate the ad8132 with a purely differential input, many of its applications call for a circuit that has a single-ended input with a differential output. for a single-ended-to-differential circuit, the r g of the input that is not driven is tied to a reference voltage. this is ground. other conditions are discussed in the following sections. in addition, the voltage at v ocm , and therefore v out, cm , is assumed to be ground. figure 67 shows a generalized schematic of such a circuit using an ad8132 with two feedback paths. for each feedback network, a feedback factor can be defined as the fraction of the output signal that is fed back to the opposite sign input. these terms are ( ) f1 g1 g1 r r r 1 + = ( ) f2 g2 g2 r r r 2 + = the feedback factor, 1, is for the side that is driven, and the feedback factor, 2, is for the side that is tied to a reference voltage (ground). note that each feedback factor can vary anywhere between 0 and 1. a single-ended-to-differential gain equation can be derived (this is true for all values of 1 and 2): ( ) () 2 1 1 g + ? = 1 2 this expression is not very intuitive, but some further examples can provide better understanding of its implications. one observation that can be made immediately is that a tolerance error in 1 does not have the same effect on gain as the same tolerance error in 2. differential amplifier without resistors (high input impedance inverting amplifier) the simplest closed-loop circuit that can be made does not require any resistors and is shown in figure 70. in this circuit, 1 is equal to 0, and 2 is equal to 1. the gain is equal to 2. a more intuitive method to figure the gain is by simple inspection. +out is connected to ?in, whose voltage is equal to the voltage at +in under equilibrium conditions. thus, +v out is equal to v in , and there is unity gain in this path. because ?out has to swing in the opposite direction from +out due to the common-mode constraint, its effect doubles the output signal and produces a gain of 2. one useful function that this circuit provides is a high input impedance inverter. if +out is ignored, there is a unity-gain, high input impedance amplifier formed from +in to ?out. most traditional op amp inverters have relatively low input impedances, unless they are buffered with another amplifier. v ocm is assumed to be at midsupply. because there is still the constraint that +v out must equal v in , changing the v ocm voltage does not change +v out (equal to v in ). therefore, the effect of changing v ocm must show up at ?out. for example, if v ocm is raised by 1 v, then ?v out must increase by 2 v. this makes v out, cm also increase by 1 v, because it is defined as the average of the two differential output voltages. this means that the gain from v ocm to the differential output is 2.
ad8132 rev. f | page 22 of 32 other 2 = 1 circuits the preceding simple configuration with 2 = 1 and its gain of 2 is the highest gain circuit that can be made under this condition. since 1 was equal to 0, only higher 1 values are possible. the circuits with higher values of 1 have gains lower than 2. however, circuits with 1 equal to 1 are not practical because they have no effective input and result in a gain of 0. to increase 1 from 0, it is necessary to add two resistors in a feed- back network. a generalized circuit that has 1 with a value higher than 0 is shown in figure 69. a couple of different convenient gains that can be created are a gain of 1, when 1 is equal to 1/3, and a gain of 0.5, when 1 equals 0.6. with 2 equal to 1 in these circuits, v ocm serves as the refer- ence voltage that measures the input voltage and the individual output voltages. in general, when v ocm is varied in circuits with unmatched feedback networks, a differential output signal is generated that is proportional to the applied v ocm voltage. varying 2 though the 2 = 1 circuit sets 2 to 1, another class of simple circuits can be made that sets 2 equal to 0. this means that there is no feedback from +out to ?in. this class of circuits is very similar to a conventional inverting op amp. however, the ad8132 circuits have an additional output and common- mode input that can be analyzed separately (see figure 71). with ?in connected to ground, +in becomes a virtual ground in the sense that the term is used for conventional op amps. both inputs must maintain the same voltage for equilibrium operation; therefore, if one is set to ground, the other is driven to ground. the input impedance can also be seen to be equal to r g , just as in a conventional op amp. in this case, however, the positive input and negative output are used for the feedback network. because a conventional op amp does not have a negative output, only its inverting input can be used for the feedback network. the ad8132 is symmetrical, there- fore, the feedback network on either side can be used to produce the same results. because +in is a summing junction, by an analogy to conven- tional op amps, the gain from v in to ?out is ?r f /r g . this holds true regardless of the voltage on v ocm , and since +out moves the same amount in the opposite direction from ?out, the overall gain is ?2(r f /r g ). v ocm still governs v out, cm , so +out must be the only output that moves when v ocm is varied. because v out, cm is the average of the two outputs, +out must move twice as far and in the same direction as v ocm to create the proper v out, cm . therefore, the gain from v ocm to +out must be 2. with 2 equal to 0 in these circuits, the gain can theoretically be set to any value from close to 0 to infinity, just as it can with a conventional op amp in the inverting mode. however, practical real-world limitations and parasitics limit the range of acceptable gain to more modest values. 1 = 0 there is yet another class of circuits where there is no feed- back from ?out to +in. this is the case where 1 = 0. the differential amplifier without a resistor described in the differential amplifier without resistors (high input impedance inverting amplifier) section meets this condition, but it was presented only with the condition that 2 = 1. recall that this circuit had a gain equal to 2. if 2 decreases in this circuit from unity, a smaller part of +v out is fed back to ?in and the gain increases (see figure 68). this circuit is very similar to a noninverting op amp configuration, except for the presence of the additional complementary output. therefore, the overall gain is twice that of a noninverting op amp or 2 (1 + r f2 /r g2 ) or 2 (1/2). once again, varying v ocm does not affect both outputs in the same way; therefore, in addition to varying v out, cm with unity gain, there is also an effect on v out, dm by changing v ocm . estimating the output noise voltage similar to the case of a conventional op amp, the differential output errors (noise and offset voltages) can be estimated by multiplying the input referred terms, at +in and ?in, by the circuit noise gain. the noise gain is defined as ? ? ? ? ? ? + = g f n r r g 1 to compute the total output referred noise for the circuit of figure 64, consideration must be given to the contribution of resistors, r f and r g . see table 11 for estimated output noise voltage densities at various closed-loop gains. table 11. recommended resi stor values and noise performance for specific gains gain r g () r f () bandwidth ?3 db (mhz) output noise ad8132 only (nv/hz) output noise ad8132 + r g , r f (nv/hz) 1 499 499 360 16 17 2 499 1.0 k 160 24.1 26.1 5 499 2.49 k 65 48.4 53.3 10 499 4.99 k 20 88.9 98.6
ad8132 rev. f | page 23 of 32 when using the ad8132 in gain configurations where 1 2, differential output noise appears due to input-referred voltage noise in the v ocm circuitry according to the following formula: ? ? ? ? ? ? ? ? + ? = 2 1 2 1 v v nocm ond 2 where v ond is the output differential noise and v nocm is the input-referred voltage noise on v ocm . calculating input impedance of the application circuit the effective input impedance of a circuit, such as that in figure 64, at +d in and ?d in , depends on whether the amplifier is being driven by a single-ended or differential signal source. for balanced differ- ential input signals, the input impedance (r in, dm ) between the inputs (+d in and ?d in ) is simply g dm in, r r = 2 in the case of a single-ended input signal (for example, if ?d in is grounded and the input signal is applied to +d in ), the input impedance becomes () ? ? ? ? ? ? ? ? ? ? ? ? + ? = f g f g dm in, r r r r r 2 1 the circuit input impedance is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor r g . input common-mode voltage range in single-supply applications the ad8132 is optimized for level-shifting ground-referenced input signals. for a single-ended input, this implies that the voltage at ?d in in figure 64 is 0 v when the amplifiers negative power supply voltage (at v?) was also set to 0 v. setting the output common-mode voltage the ad8132s v ocm pin is internally biased at a voltage approx- imately equal to the midsupply point (average value of the voltage on v+ and v?). relying on this internal bias results in an output common-mode voltage that is within approximately 100 mv of the expected value. in cases where more accurate control of the output common-mode level is required, it is best practice that an external source or resistor divider (with r source < 10 k) be used. the output common-mode offset values in the specifications section assume the v ocm input is driven by a low impedance voltage source. driving a capacitive load a purely capacitive load can react with the pin and bond wire inductance of the ad8132, resulting in high frequency ringing in the pulse response. one way to minimize this effect is to place a small capacitor across each of the feedback resistors. the added capacitance must be small to avoid destabilizing the amplifier. an alternative technique is to place a small resistor in series with the amplifier outputs, as shown in figure 60. open-loop gain and phase open-loop gain and phase plots are shown in figure 65 and figure 66. ?20 ?10 0 10 20 30 40 50 60 0.1 1 10 100 1000 frequency (mhz) open-loop gain (db) r l, dm = 2k ? 01035-083 figure 65. open-loop gain plot ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 0.1 1 10 100 1000 frequency (mhz) open-loop phase (degrees) r l, dm = 2k ? 01035-084 figure 66. open-loop phase plot
ad8132 rev. f | page 24 of 32 layout, grounding, and bypassing as a high speed part, the ad8132 is sensitive to the pcb envi- ronment in which it operates. realizing its superior specifications requires attention to various details of good high speed pcb design. the first requirement is a good solid ground plane that covers as much of the board area around the ad8132 as possible. the only exception to this is that the two input pins (pin 1 and pin 8) are kept a few millimeters from the ground plane and that ground be removed from inner layers and the opposite side of the board under the input pins. this minimizes the stray capacitance on these nodes and helps preserve the gain flatness vs. the frequency. bypass the power supply pins as close as possible to the device to the nearby ground plane and use good high frequency ceramic chip capacitors. do this bypassing with a capacitance value of 0.01 f to 0.1 f for each supply. farther away, provide low fre- quency bypassing with 10 f tantalum capacitors from each supply to ground. keep the signal routing short and direct to avoid parasitic effects. wherever there are complementary signals, a symmetrical layout with matched lengths must be provided to the extent possible to maximize the balance performance. when running differ- ential signals over a long distance, place the traces on the pcb close together or twist together any differential wiring to minimize the area of the loop that is formed. this reduces the radiated energy and makes the circuit less susceptible to interference. circuits r f1 + r f2 r g1 r g2 01035-065 figure 67. typical four-resistor feedback circuit + r f2 r g2 v in 01035-066 figure 68. typical circuit with 1 = 0 r f1 + r g1 01035-067 figure 69. typical circuit with 2 = 1 + v in 01035-068 figure 70. g = 2 circuit with 1 = 0, without resistors r f1 + r g1 v in 01035-069 figure 71. typical circuit with 2 = 0
ad8132 rev. f | page 25 of 32 applications analog-to-digital driver many of the newer high speed adcs are single-supply and have differential inputs. thus, the driver for these devices is able to convert from a single-ended signal to a differential signal and provide output common-mode level shifting in addition to having low distortion and noise. the ad8132 conveniently performs these functions when driving the ad9203 , a 10-bit, 40 msps adc. in figure 73, a 1 v p-p signal drives the input of an ad8132 configured for unity gain. both the ad8132 and the ad9203 are powered from a single 3 v supply. a voltage divider biases v ocm at midsupply and in turn drives v out, cm to half of the supply voltage. this is within the common-mode range of the ad9203. between the adc and the driver is a 1-pole, differential filter that helps to filter some of the noise and assists the switched-capacitor inputs of the adc. each of the adc inputs is driven by a 0.5 v p-p signal that ranges from 1.25 v dc to 1.75 v dc. figure 72 is an fft plot of the performance of the circuit when running at a clock rate of 40 msps and an input frequency of 2.5 mhz. balanced cable driver when driving a twisted pair cable, it is desirable to drive only a pure differential signal onto the line. if the signal is purely differ- ential (that is, fully balanced), and the transmission line is twisted and balanced, there is minimum radiation of any signal. the complementary electrical fields are confined mostly to the space between the two twisted conductors and does not signif- icantly radiate out from the cable. the current in the cable creates magnetic fields that radiate to some degree. however, the amount of radiation is mitigated by the twists, because for each twist, the two adjacent twists have an opposite polarity magnetic field. if the twist pitch is tight enough, these small magnetic field loops contain most of the magnetic flux, and the magnetic farfield strength is negligible. 10 0 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 2nd 3rd 4th 5th 7th 8th 9th 6th f s = 40mhz f in = 2.5mhz input frequency (mhz) output (dbc) fund 01035-071 figure 72. ftt response for ad8132 driving ad9203 3 v 0.1f 10f + 3v 348 ? 0.1f 348 ? 49.9 ? 348 ? 24.9 ? 10k ? 10k ? 1v p-p 348 ? 60.4 ? 60.4 ? 20pf 20pf ainn ainp avdd drvdd avss drvss ad9203 digital outputs 3v 0.1f 0.1f ad8132 8 2 1 3 5 6 4 25 26 28 27 1 2 01035-070 figure 73. ad8132 driving ad9203, a 10-bit, 40 msps adc
ad8132 rev. f | page 26 of 32 499 ? 523 ? 1k ? 1k ? 10f + +5 v ad8132 0.1f 49.9 ? 50 ? s ource 0.1f + 0.1f 10f ?5v 49.9 ? 49.9 ? twisted pair 100 ? 1 2 3 4 7 5 ad830 + 0.1f 10f ?5v 10f + +5v 0.1f v out 01035-072 figure 74. balanced line driver and receiver using ad8132 and ad830 any imbalance in the differential drive signal appears as a common-mode signal on the cable. this is the equivalent of a single wire that is driven with the common-mode signal. in this case, the wire acts as an antenna and radiates. thus, to minimize radiation when driving differential twisted pair cables, make sure the differential drive signal is well balanced. the common-mode feedback loop in the ad8132 helps to min- imize the amount of common-mode voltage at the output, and can therefore be used to create a well-balanced differential line driver. figure 74 shows an application that uses an ad8132 as a balanced line driver and an ad830 as a differential receiver con- figured for unity gain. this circuit was operated with 10 meters of category 5 cable. transmit equalizer any length of transmission line attenuates the signals it carries. this effect is worse at higher frequencies than at lower frequencies. one way to compensate for this is to provide an equalizer circuit that boosts the higher frequencies in the transmitter circuit, so that at the receive end of the cable, the attenuation effects are diminished. by lowering the impedance of the r g component of the feed- back network at a higher frequency, the gain can be increased at a high frequency. figure 75 shows the gain of a two-line driver that has its r g resistors shunted by 10 pf capacitors. the effect of this is shown in the frequency response plot of figure 76. 249 ? 49.9 ? 10pf 499 ? 10pf 249 ? 24.9 ? v in 49.9 ? 499 ? 49.9 ? 100 ? v out 01035-073 figure 75. frequency boost circuit 1 1000 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 v out / v in (db) 10 100 frequency (mhz) 01035-074 figure 76. frequency response for transmit boost circuit low-pass differential filter similar to an op amp, various types of active filters can be created with the ad8132. these can have single-ended inputs and differ- ential outputs that can provide an antialias function when driving a differential adc. figure 77 is a schematic of a low-pass, multiple feedback filter. the active section contains two poles, and an additional pole is added at the output. the filter was designed to have a ?3 db frequency of 1 mhz. the actual ?3 db frequency was measured to be 1.12 mhz, as shown in figure 78. 33pf 2.15k ? ? 953 ? 33pf 2.15k ? 100pf 100pf 2k ? 2k ? 24.9 ? 49.9 ? 549 ? 54 ? 200pf 200pf v in v out 01035-075 figure 77. 1 mhz, 3-pole differential output, low-pass, multiple feedback filter
ad8132 rev. f | page 27 of 32 frequency (hz) 10 10k 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 100k 1m 10m 100m v out / v in (db) 01035-076 figure 78. frequency response of 1 mhz low-pass filter high common-mode output impedance amplifier changing the connection to v ocm (pin 2) can change the common- mode from low impedance to high impedance. if v ocm is actively set to a particular voltage, the ad8132 tries to force v out, cm to the same voltage with a relatively low output impedance. all the previous analysis assumed that this output impedance is arbitrarily low enough to drive the load condition in the circuit. however, there are some applications that benefit from a high common-mode output impedance. this is accomplished with the circuit shown in figure 79. r g 348 ? r f 348 ? r f 348 ? r g 348 ? 10 ? 10 ? 1k ? 1k ? 49.9 ? 49.9 ? 0 1035-077 figure 79. high common-mode, output impedance, differential amplifier v ocm is driven by a resistor divi der that measures the output common-mode voltage. thus, the common-mode output voltage takes on the value that is set by the driven circuit. in this case, it comes from the center point of the termination at the receive end of a 10 meter length of category 5 twisted pair cable. if the receive end common-mode voltage is set to ground, it is well defined at the receive end. any common-mode signal that is picked up over the cable length due to noise appears at the transmit end and must be absorbed by the transmitter. thus, it is important that the transmitter have adequate common-mode output range to absorb the full amplitude of the common-mode signal coupled onto the cable and therefore prevent clipping. another way to look at this is that the circuit performs what is sometimes called transformer action. one main difference is that the ad8132 passes dc while transformers do not. a transformer can also be easily configured to have either a high or low common-mode output impedance. if the transformers center tap is connected to a solid voltage reference, it sets the common- mode voltage on the secondary side of the transformer. in this case, if one of the differential outputs is grounded, the other output has half of the differential output signal. this keeps the common-mode voltage at ground, where it is required to be due to the center tap connection. this is analogous to the ad8132 operating with a low output impedance common-mode (see figure 80). v diff v ocm 01035-078 figure 80. transformer with low output impedance secondary set at v ocm if the center tap of the secondary of a transformer is allowed to float as shown in figure 81 (or if there is no center tap), the transformer has a high common-mode output imped- ance. this means that the common mode of the secondary is determined by what it is connected to and not by anything to do with the transformer itself. if one of the differential ends of the transformer is grounded, the other end swings with the full output voltage. this means that the common mode of the output voltage is one-half of the differential output voltage. however, this shows that the common mode is not forced via a low impedance to a given voltage. the common-mode output voltage can be easily changed to any voltage through its other output terminals. the ad8132 can exhibit the same performance when one of the outputs in figure 79 is grounded. the other output swings at the full differential output voltage. the common-mode signal is measured by the voltage divider across the outputs and input to v ocm . this, then, drives v out, cm to the same level. at higher frequencies, it is important to minimize the capacitance on the v ocm node; otherwise, phase shifts can compromise the perfor- mance. the voltage divider resistances can also be lowered for better frequency response. v diff nc 01035-079 figure 81. transformer with high output impedance secondary
ad8132 rev. f | page 28 of 32 full-wave rectifier the balanced outputs of the ad8132, along with a couple of schottky diodes, can create a very high speed, full-wave rectifier. such circuits are useful for measuring ac voltages and other computational tasks. figure 82 shows the configuration of such a circuit. each of the ad8132 outputs drives the anode of an hp2835 schottky diode. these schottky diodes were chosen for their high speed operation. at lower frequencies (approximately lower than 10 mhz), a silicon signal diode, such as a 1n4148, can be used. the cathodes of the two diodes are connected together, and this output node is con- nected to ground by a 100 resistor. r g1 348 ? r f1 348 ? r f2 348 ? r g2 348 ? +5 v ?5v r l 100 ? r t2 24.9 ? r t1 49.9 ? v in hp2835 v out +5v cr1 10k ? 01035-080 figure 82. full-wave rectifier operate the diodes such that they are slightly forward-biased when the differential output voltage is 0. for the schottky diodes, this is approximately 400 mv. the forward biasing is conveniently adjusted by cr1, which, in this circuit, raises and lowers v out, cm without creating a differential output voltage. one advantage of this circuit is that the feedback loop is never momentarily opened while the diodes reverse their polarity within the loop. this scheme is sometimes used for full-wave rectifiers that use conventional op amps. these conventional circuits do not work well at frequencies above approximately 1 mhz. if there is not enough forward bias (v out, cm too low), the lower sharp cusps of the full-wave rectified output waveform are rounded off. in addition, as the frequency increases, there tends to be some rounding of the lower cusps. the forward bias can be increased to yield sharper cusps at higher frequencies. there is not a reliable, entirely quantifiable means to measure the performance of a full-wave rectifier. since the ideal wave- form has periodic sharp discontinuities, it has (mostly even) harmonics that have no upper bound on the frequency. how- ever, for a practical circuit, as the frequency increases, the higher harmonics become attenuated and the sharp cusps that are present at low frequencies become significantly rounded. when running the circuit at a frequency up to 300 mhz, though it stays functional, the major harmonic that remains in the output is the second. this looks like a sine wave at 600 mhz. figure 83 is an oscilloscope plot of the output when driven by a 100 mhz, 2.5 v p-p input. sometimes a second harmonic generator is useful for creating a clock to oversample a dac by a factor of two. if the output of this circuit is run through a low-pass filter, it can be used as a second harmonic generator. 100mv 2ns 1v 01035-081 figure 83. full-wave rectifier response with 100 mhz input
ad8132 rev. f | page 29 of 32 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 060506-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 84. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 85. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model temperature range package description pa ckage option branding ordering quantity ad8132ar ?40c to +125c 8-lead soic_n r-8 ad8132ar-reel ?40c to +125c 8-lead so ic_n, 13" tape and reel r-8 2,500 ad8132ar-reel7 ?40c to +125c 8-lead so ic_n, 7" tape and reel r-8 1,000 ad8132arz 1 ?40c to +125c 8-lead soic_n r-8 ad8132arz-rl 1 ?40c to +125c 8-lead soic_n, 13" tape and reel r-8 2,500 AD8132ARZ-R7 1 ?40c to +125c 8-lead soic_n, 7" tape and reel r-8 1,000 ad8132arm ?40c to +125c 8-lead msop rm-8 hma ad8132arm-reel ?40c to +125c 8-lead msop, 13" tape and reel rm-8 hma 3,000 ad8132arm-reel7 ?40c to +125c 8-lead msop, 7" tape and reel rm-8 hma 1,000 ad8132armz 1 ?40c to +125c 8-lead msop rm-8 hma# ad8132armz-reel 1 ?40c to +125c 8-lead msop, 13" tape and reel rm-8 hma# 3,000 ad8132armz-reel7 1 ?40c to +125c 8-lead msop, 7" tape and reel rm-8 hma# 1,000 1 z = pb-free part, # denotes lead-free product may be top or bottom marked.
ad8132 rev. f | page 30 of 32 notes
ad8132 rev. f | page 31 of 32 notes
ad8132 rev. f | page 32 of 32 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c01035C0C11/06(f)

▲Up To Search▲

Price & Availability of AD8132ARZ-R7

	To Download AD8132ARZ-R7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .